Data Sheet

564
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
27.8.2.7 Status
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property: Write-Synchronized
z Bits 15:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 10 – LENERR: Transaction Length Error
This bit is set when automatic length is used for a DMA transaction and the slave sends a NACK before
ADDR.LEN bytes have been written by the master.
Writing a one to this bit location will clear STATUS.LENERR. This flag is automatically cleared when writing to the
ADDR register.
Writing a zero to this bit has no effect.
This bit is not write-synchronized.
z Bit 9 – SEXTTOUT: Slave SCL Low Extend Time-Out
This bit is set if a slave SCL low extend time-out occurs.
Writing a one to this bit location will clear STATUS.SEXTTOUT. Normal use of the I
2
C interface does not require
the STATUS.SEXTTOUT flag to be cleared by this method. This flag is automatically cleared when writing to the
ADDR register.
Writing a zero to this bit has no effect.
This bit is not write-synchronized.
z Bit 8 – MEXTTOUT: Master SCL Low Extend Time-Out
This bit is set if a master SCL low time-out occurs.
Writing a one to this bit location will clear STATUS.MEXTTOUT. Normal use of the I
2
C interface does not require
the STATUS.MEXTTOUT flag to be cleared by this method. This flag is automatically cleared when writing to the
ADDR register.
Writing a zero to this bit has no effect.
This bit is not write-synchronized.
z Bit 7 – CLKHOLD: Clock Hold
The Master Clock Hold flag (STATUS.CLKHOLD) is set when the master is holding the SCL line low, stretching
the I
2
C clock. Software should consider this bit a read-only status flag that is set when INTFLAG.SB or INT-
Bit151413121110 9 8
LENERR SEXTTOUT MEXTTOUT
Access R R R R R R/W R/W R/W
Reset00000000
Bit76543210
CLKHOLD LOWTOUT BUSSTATE[1:0]
RXNACK ARBLOST BUSERR
Access R R/W R R/W R R R/W R/W
Reset00000000