Data Sheet

557
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
can be written at the same time, and then the acknowledge action will be updated before the command is
triggered.
Commands can only be issued when the Slave on Bus interrupt flag (INTFLAG.SB) or Master on Bus interrupt flag
(INTFLAG.MB) is one.
If CMD 0x1 is issued, a repeated start will be issued followed by the transmission of the current address in
ADDR.ADDR. If another address is desired, ADDR.ADDR must be written instead of the CMD bits. This will trigger
a repeated start followed by transmission of the new address.
Issuing a command will set STATUS.SYNCBUSY.
Table 27-12. Command Description
These bits are not enable-protected.
z Bits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 9 – QCEN: Quick Command Enable
Setting the Quick Command Enable bit (QCEN) enables quick command.
0: Quick Command is disabled.
1: Quick Command is enabled.
This bit is not write-synchronized.
z Bit 8 – SMEN: Smart Mode Enable
This bit enables smart mode. When smart mode is enabled, acknowledge action is sent when DATA.DATA is
read.
0: Smart mode is disabled.
1: Smart mode is enabled.
This bit is not write-synchronized.
z Bits 7:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
CMD[1:0] Direction Action
0x0 X (No action)
0x1 X Execute acknowledge action succeeded by repeated Start
0x2
0 (Write) No operation
1 (Read) Execute acknowledge action succeeded by a byte read operation
0x3 X Execute acknowledge action succeeded by issuing a stop condition