Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is
complete.
This bit is not enable-protected.
z Bit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SER-
COM will be disabled.
Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded.
Any register write access during the ongoing reset will result in an APB error. Reading
any register will return the reset value of the register.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.