Data Sheet

554
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
SB or MB will be set as normal, but CLKHOLD will be release. The MEXTTOUT and BUSERR status bits will
be set.
0: Time-out disabled
1: Time-out enabled
This bit is not synchronized.
z Bits 21:20 – SDAHOLD[1:0]: SDA Hold Time
These bits define the SDA hold time with respect to the negative edge of SCL.
Table 27-11. SDA Hold Time
These bits are not synchronized.
z Bits 19:17 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 16 – PINOUT: Pin Usage
This bit set the pin usage to either two- or four-wire operation:
0: 4-wire operation disabled.
1: 4-wire operation enabled.
This bit is not synchronized.
z Bits 15:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 7 – RUNSTDBY: Run in Standby
This bit defines the functionality in standby sleep mode.
0: GCLK_SERCOMx_CORE is disabled and the I
2
C master will not operate in standby sleep mode.
1: GCLK_SERCOMx_CORE is enabled in all sleep modes allowing the master to operate in standby sleep mode.
This bit is not synchronized.
z Bits 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 4:2 – MODE[2:0]: Operating Mode
These bits must be written to 0x5 to select the I
2
C master serial communication interface of the SERCOM.
These bits are not synchronized.
z Bit 1 – ENABLE: Enable
0: The peripheral is disabled.
1: The peripheral is enabled.
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Sync-
Value Name Description
0x0 DIS Disabled
0x1 75NS 50-100ns hold time
0x2 450NS 300-600ns hold time
0x3 600NS 400-800ns hold time