Data Sheet
553
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Enabling this option is necessary for SMBus compatibility, but can also be used in a non-SMBus set-up.
Table 27-9. Inactive Timout
Calculated time-out periods are based on a 100kHz baud rate.
These bits are not synchronized.
z Bit 27– SCLSM: SCL Clock Stretch Mode
This bit controls when SCL will be stretch for software interaction.
0: SCL stretch according to Figure 27-7.
1: SCL stretch only after ACK bit.
This bit is not synchronized.
z Bit 26– Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bits 25:24 – SPEED[1:0]: Transfer Speed
These bits define bus speed.
Table 27-10. Transfer Speed
These bits are not synchronized.
z Bit 23 – SEXTTOEN: Slave SCL Low Extend Time-Out
This bit enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms
from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state
machine. Any interrupts set at the time of time-out will remain set. If the address was recognized, PREC will
be set when a STOP is received.
0: Time-out disabled
1: Time-out enabled
This bit is not synchronized.
z Bit 22 – MEXTTOEN: Master SCL Low Extend Time-Out
This bit enables the master SCL low extend time-out. If SCL is cumulatively held low for greater than 10ms from
START-to-ACK, ACK-to-ACK, or ACK-to-STOP the master will release its clock hold if enabled, and complete the
current transaction. A STOP will automatically be transmitted.
Value Name Description
0x0 DIS Disabled
0x1 55US 5-6 SCL cycle time-out (50-60µs)
0x2 105US 10-11 SCL cycle time-out (100-110µs)
0x3 205US 20-21 SCL cycle time-out (200-210µs)
Value Description
0x0 Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz
0x1 Fast-mode Plus (Fm+) up to 1 MHz
0x2 High-speed mode (Hs-mode) up to 3.4 MHz
0x3 Reserved