Data Sheet

547
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
0: No SCL low time-out has occurred.
1: SCL low time-out has occurred.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the status.
z Bit 5 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bit 4 – SR: Repeated Start
When INTFLAG.AMATCH is raised due to an address match, SR indicates a repeated start or start condition.
0: Start condition on last address match
1: Repeated start condition on last address match
This flag is only valid while the INTFLAG.AMATCH flag is one.
z Bit 3 – DIR: Read / Write Direction
The Read/Write Direction (STATUS.DIR) bit stores the direction of the last address packet received from a master.
0: Master write operation is in progress.
1: Master read operation is in progress.
z Bit 2 – RXNACK: Received Not Acknowledge
This bit indicates whether the last data packet sent was acknowledged or not.
0: Master responded with ACK.
1: Master responded with NACK.
z Bit 1 – COLL: Transmit Collision
If set, the I
2
C slave was not able to transmit a high data or NACK bit, the I
2
C slave will immediately release the
SDA and SCL lines and wait for the next packet addressed to it.
This flag is intended for the SMBus address resolution protocol (ARP). A detected collision in non-ARP situations
indicates that there has been a protocol violation, and should be treated as a bus error.
Note that this status will not trigger any interrupt, and should be checked by software to verify that the data were
sent correctly. This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing
0x3 to CTRLB.CMD), or INTFLAG.AMATCH is cleared.
0: No collision detected on last data byte sent.
1: Collision detected on last data byte sent.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the status.
z Bit 0 – BUSERR: Bus Error
The Bus Error bit (STATUS.BUSERR) indicates that an illegal bus condition has occurred on the bus, regardless
of bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected
on the I
2
C bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If
a time-out occurs during a frame, this is also considered a protocol violation, and will set STATUS.BUSERR.
This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to
CTRLB.CMD) or INTFLAG.AMATCH is cleared.
0: No bus error detected.
1: Bus error detected.
Writing a one to this bit will clear the status.
Writing a zero to this bit has no effect.