Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181G–SAM-D21_Datasheet–09/2015

27.8.1.5 Interrupt Flag Status and Clear

Name: INTFLAG

Offset: 0x18

Reset: 0x00

Property: -

z Bit 7– ERROR: Error

This flag is cleared by writing a one to it.

This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the

STATUS register. Errors that will set this flag are SEXTTOUT, LOWTOUT, COLL, and BUSERR.

Writing a

zero to this bit has no effect.

Writing a one to this bit will clear the flag.

z Bits 6:3 – Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to

zero when this register is written. These bits will always return zero when read.

z Bit 2 – DRDY: Data Ready

This flag is set when a I

C slave byte transmission is successfully completed.

The flag is cleared by hardware when either:

z Writing to the DATA register.

z Reading the DATA register with smart mode enabled.

z Writing a valid command to the CMD register.

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Data Ready interrupt flag. Optionally, the flag can be cleared manually by writ-

ing a one to INTFLAG.DRDY.

z Bit 1 – AMATCH: Address Match

This flag is set when the I

C slave address match logic detects that a valid address has been received.

The flag is cleared by hardware when CTRL.CMD is written.

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Address Match interrupt flag. Optionally the flag can be cleared manually by

writing a one to INTFLAG.AMATCH. When cleared, an ACK/NACK will be sent according to CTRLB.ACKACT.

z Bit 0 – PREC: Stop Received

This flag is set when a stop condition is detected for a transaction being processed. A stop condition detected

between a bus master and another slave will not set this flag.

This flag is cleared by hardware after a command is issued on the next address match.

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Stop Received interrupt flag. Optionally, the flag can be cleared manually by

writing a one to INTFLAG.PREC.

Bit

76543210

ERROR

DRDY AMATCH PREC

Access

R/WRRRRR/WR/WR/W

Reset

00000000