Data Sheet

544
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
27.8.1.4 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: Write-Protected
z Bit 7 – ERROR: Error Interrupt Enable
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
z Bits 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 2 – DRDY: Data Ready Interrupt Enable
0: The Data Ready interrupt is disabled.
1: The Data Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Data Ready bit, which enables the Data Ready interrupt.
z Bit 1 – AMATCH: Address Match Interrupt Enable
0: The Address Match interrupt is disabled.
1: The Address Match interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Address Match Interrupt Enable bit, which enables the Address Match interrupt.
z Bit 0 – PREC: Stop Received Interrupt Enable
0: The Stop Received interrupt is disabled.
1: The Stop Received interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Stop Received bit, which enables the Stop Received interrupt.
Bit76543210
ERROR
DRDY AMATCH PREC
Access R/W R R R R R/W R/W R/W
Reset00000000