Data Sheet
539
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z Bit 16 – PINOUT: Pin Usage
This bit sets the pin usage to either two- or four-wire operation:
0: 4-wire operation disabled
1: 4-wire operation enabled
This bit is not synchronized.
z Bits 15:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 7 – RUNSTDBY: Run in Standby
This bit defines the functionality in standby sleep mode.
0: Disabled – All reception is dropped.
1: Wake on address match, if enabled.
This bit is not synchronized.
z Bits 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 4:2 – MODE[2:0]: Operating Mode
These bits must be written to 0x04 to select the I
2
C slave serial communication interface of the SERCOM.
These bits are not synchronized.
z Bit 1 – ENABLE: Enable
0: The peripheral is disabled.
1: The peripheral is enabled.
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Syn-
chronization busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the
operation is complete.
This bit is not enable-protected.
z Bit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SER-
COM will be disabled.
Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded.
Any register write access during the ongoing reset will result in an APB error. Reading
any register will return the reset value of the register.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.