Data Sheet

538
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
1: SCL stretch only after ACK bit according to Figure 27-10.
This bit is not synchronized.
z Bit 26– Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bits 25:24 – SPEED[1:0]: Transfer Speed
These bits define bus speed.
Table 27-5. Transfer Speed
These bits are not synchronized.
z Bit 23 – SEXTTOEN: Slave SCL Low Extend Time-Out
This bit enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms
from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state
machine. Any interrupts set at the time of time-out will remain set. If the address was recognized, PREC will
be set when a STOP is received.
0: Time-out disabled
1: Time-out enabled
This bit is not synchronized.
z Bit 22 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bits 21:20 – SDAHOLD[1:0]: SDA Hold Time
These bits define the SDA hold time with respect to the negative edge of SCL.
Table 27-6. SDA Hold Time
These bits are not synchronized.
z Bits 19:17 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Value Description
0x0 Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz
0x1 Fast-mode Plus (Fm+) up to 1 MHz
0x2 High-speed mode (Hs-mode) up to 3.4 MHz
0x3 Reserved
Value Name Description
0x0 DIS Disabled
0x1 75 50-100ns hold time
0x2 450 300-600ns hold time
0x3 600 400-800ns hold time