Data Sheet

528
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
27.6.4 DMA, Interrupts and Events
27.6.4.1 DMA Operation
Smart mode (CTRLB.SMEN) must be enabled for DMA operation.
Slave DMA
When using the I
2
C slave with DMA, an address match will cause the address interrupt flag (INTFLAG.ADDRMATCH) to
be raised. After the interrupt has been serviced, data transfer will be performed through DMA.
The I
2
C slave generates the following requests:
z Write data received (RX): The request is set when master write data is received. The request is cleared when
DATA is read.
z Read data needed for transmit (TX): The request is set when data is needed for a master read operation. The
request is cleared when DATA is written.
Master DMA
When using the I
2
C master with DMA, the ADDR register must be written with the desired address (ADDR.ADDR),
transaction length (ADDR.LEN), and transaction length enable (ADDR.LENEN). When ADDR.LENEN is written to 1
Table 27-1. Module Request for SERCOM I
2
C Slave
Condition Interrupt request Event output Event input DMA request
DMA request is
cleared
Data Ready x
Data received
(Slave receive
mode)
x
when data is
read
Data needed for
transmit (Slave
transmit mode)
x
when data is
written
Address Match x
Stop received x
Error x
Table 27-2. Module Request for SERCOM I
2
C Master
Condition Interrupt request Event output Event input DMA request
DMA request is
cleared
Master on Bus x
Slave on Bus x
Data received
(Master receive
mode)
x
when data is
read
Data needed for
transmit (Master
transmit mode)
x
when data is
written
Error x