Data Sheet
519
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Figure 27-6. I
2
C Master Behavioral Diagram (SCLSM=0)
In the second strategy (SCLSM=1), interrupts only occur after the ACK bit as shown in Figure 27-7. This strategy can be
used when it is not necessary to check DATA before acknowledging.
Note that setting SCLSM to 1 is required for High-speed mode.
IDLE S BUSYBUSY P
Sr
P
M3
M3
M2
M2
M1
M1
R DATA
ADDRESS
W
A/ADATA
Wait for
IDLE
APPLICATION
S
W
S
W
Sr
P
M3
M2
BUSY
M4
A
S
W
A/A
A/A
A/A
M4
A
IDLE
IDLE
MASTER READ INTERRUPT + SCL HOLD
MASTER WRITE INTERRUPT + SCL HOLD
S
W
S
W
S
W
BUSYR/W
S
W
Software interaction
The master provides data
on the bus
Addressed slave provides
data on the bus
A
A
R/W
BUSY
M4