Data Sheet

497
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z Bit 16 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bits 15:14 – AMODE: Address Mode
These bits set the slave addressing mode when the frame format (CTRLA.FORM) with address is used. They are
unused in master mode.
Table 26-9. Address Mode
z Bit 13 – MSSEN: Master Slave Select Enable
This bit enables hardware slave select (_SS) control.
0: Hardware _SS control is disabled.
1: Hardware _SS control is enabled.
z Bits 12:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 9 – SSDE: Slave Select Low Detect Enable
This bit enables wake up when the slave select (_SS) pin transitions from high to low.
0: _SS low detector is disabled.
1: _SS low detector is enabled.
z Bits 8:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 6 – PLOADEN: Slave Data Preload Enable
Setting this bit will enable preloading of the slave shift register when there is no transfer in progress. If the _SS line
is high when DATA is written, it will be transferred immediately to the shift register.
z Bits 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 2:0 – CHSIZE[2:0]: Character Size
Table 26-10. Character Size
AMODE[1:0] Name Description
0x0 MASK ADDRMASK is used as a mask to the ADDR register
0x1 2_ADDRS The slave responds to the two unique addresses in ADDR and ADDRMASK
0x2 RANGE
The slave responds to the range of addresses between and including ADDR
and ADDRMASK. ADDR is the upper limit
0x3 Reserved
CHSIZE[2:0] Name Description
0x0 8BIT 8 bits
0x1 9BIT 9 bits
0x2-0x7 Reserved