Data Sheet

496
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
26.8.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: Write-Protected, Enable-Protected
z Bits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 17 – RXEN: Receiver Enable
0: The receiver is disabled or being enabled.
1: The receiver is enabled or it will be enabled when SPI is enabled.
Writing a zero to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from
ongoing receptions will be lost and STATUS.BUFOVF will be cleared.
Writing a one to CTRLB.RXEN when the SPI is disabled will set CTRLB.RXEN immediately. When the SPI is
enabled, CTRLB.RXEN will be cleared, SYNCBUSY.CTRLB will be set and remain set until the receiver is
enabled. When the receiver is enabled CTRLB.RXEN will read back as one.
Writing a one to CTRLB.RXEN when the SPI is enabled will set SYNCBUSY.CTRLB, which will remain set until
the receiver is enabled, and CTRLB.RXEN will read back as one.
This bit is not enable-protected.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
RXEN
AccessRRRRRRR/WR
Reset00000000
Bit151413121110 9 8
AMODE[1:0]
MSSEN SSDE
Access R/W R/W R/W R R R R/W R
Reset00000000
Bit76543210
PLOADEN CHSIZE[2:0]
Access R R/W R R R R/W R/W R/W
Reset00000000