Data Sheet

494
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z Bit 17:16 – DOPO: Data Out Pinout
This bit defines the available pad configurations for data out (DO) and the serial clock (SCK). In slave operation,
the slave select line (_SS) is controlled by DOPO, while in master operation the _SS line is controlled by the port
configuration.
In master operation, DO is MOSI.
In slave operation, DO is MISO.
These bits are not synchronized.
Table 26-7. Data Out Pinout
z Bits 15:9 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 8 – IBON: Immediate Buffer Overflow Notification
This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs.
0: STATUS.BUFOVF is asserted when it occurs in the data stream.
1: STATUS.BUFOVF is asserted immediately upon buffer overflow.
This bit is not synchronized.
z Bit 7 – RUNSTDBY: Run In Standby
This bit defines the functionality in standby sleep mode.
These bits are not synchronized.
Table 26-8. Run In Standby Configuration
z Bits 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 4:2 – MODE: Operating Mode
These bits must be written to 0x2 or 0x3 to select the SPI serial communication interface of the SERCOM.
0x2: SPI slave operation
0x3: SPI master operation
These bits are not synchronized.
z Bit 1 – ENABLE: Enable
0: The peripheral is disabled or being disabled.
DOPO DO SCK Slave_SS Master_SS
0x0 PAD[0] PAD[1] PAD[2] System configuration
0x1 PAD[2] PAD[3] PAD[1] System configuration
0x2 PAD[3] PAD[1] PAD[2] System configuration
0x3 PAD[0] PAD[3] PAD[1] System configuration
RUNSTDBY Slave Master
0x0
Disabled. All reception is dropped,
including the ongoing transaction.
Generic clock is disabled when ongoing transaction is
finished. All interrupts can wake up the device.
0x1 Wake on Receive Complete interrupt.
Generic clock is enabled while in sleep modes. All
interrupts can wake up the device.