Data Sheet

472
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
25.8.8 Status
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property:
z Bits 15:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 5 – COLL: Collision Detected
This bit is cleared by writing a one to the bit or by disabling the receiver.
This bit is set when collision detection is enabled (CTRLB.COLDEN) and a collision is detected.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
z Bit 4 – ISF: Inconsistent Sync Field
This bit is cleared by writing a one to the bit or by disabling the receiver.
This bit is set when the frame format is set to auto-baud (CTRLA.FORM) and a sync field not equal to 0x55 is
received.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
z Bit 3 – CTS: Clear to Send
This bit indicates the current level of the CTS pin when flow control is enabled (CTRLA.TXPO).
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
z Bit 2 – BUFOVF: Buffer Overflow
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
This bit is cleared by writing a one to the bit or by disabling the receiver.
This bit is set when a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full,
there is a new character waiting in the receive shift register and a new start bit is detected.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
z Bit 1 – FERR: Frame Error
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
Bit151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
COLL ISF CTS BUFOVF FERR PERR
Access R R R/W R/W R R/W R/W R/W
Reset00000000