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Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Writing a one to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete
interrupt.
z Bit 1 – TXC: Transmit Complete Interrupt Enable
0: Transmit Complete interrupt is disabled.
1: Transmit Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Complete Interrupt Enable bit, which disables the Receive Complete
interrupt.
z Bit 0 – DRE: Data Register Empty Interrupt Enable
0: Data Register Empty interrupt is disabled.
1: Data Register Empty interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register
Empty interrupt.