Data Sheet

461
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
25.8.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: Enable-Protected, Write-Protected, Write-Synchronized
z Bits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 17 – RXEN: Receiver Enable
0: The receiver is disabled or being enabled.
1: The receiver is enabled or will be enabled when the USART is enabled.
Writing a zero to this bit will disable the USART receiver. Disabling the receiver will flush the receive buffer and
clear the FERR, PERR and BUFOVF bits in the STATUS register.
Writing a one to CTRLB.RXEN when the USART is disabled will set CTRLB.RXEN immediately. When the USART
is enabled, CTRLB.RXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the receiver is
enabled. When the receiver is enabled, CTRLB.RXEN will read back as one.
Writing a one to CTRLB.RXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set
until the receiver is enabled, and CTRLB.RXEN will read back as one.
This bit is not enable-protected.
z Bit 16 – TXEN: Transmitter Enable
0: The transmitter is disabled or being enabled.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
RXEN TXEN
AccessRRRRRRR/WR/W
Reset00000000
Bit151413121110 9 8
PMODE ENC SFDE COLDEN
Access R R R/W R R R/W R/W R/W
Reset00000000
Bit76543210
SBMODE CHSIZE[2:0]
Access R R/W R R R R/W R/W R/W
Reset00000000