Data Sheet

460
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
0: STATUS.BUFOVF is asserted when it occurs in the data stream.
1: STATUS.BUFOVF is asserted immediately upon buffer overflow.
z Bit 7 – RUNSTDBY: Run In Standby
This bit defines the functionality in standby sleep mode.
This bit is not synchronized.
Table 25-11. Run In Standby
z Bits 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 4:2 – MODE: Operating Mode
These bits must be written to 0x0 or 0x1 to select the USART serial communication interface of the SERCOM.
0x0: USART with external clock.
0x1: USART with internal clock.
These bits are not synchronized.
z Bit 1 – ENABLE: Enable
0: The peripheral is disabled or being disabled.
1: The peripheral is enabled or being enabled.
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Syn-
chronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation
is complete.
This bit is not enable-protected.
z Bit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SER-
COM will be disabled.
Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded.
Any register write access during the ongoing reset will result in an APB error. Reading
any register will return the reset value of the register.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.
RUNSTDBY External Clock Internal Clock
0x0
External clock is disconnected when
ongoing transfer is finished. All
reception is dropped.
Generic clock is disabled when ongoing transfer is
finished. The device can wake up on Receive Start or
Transfer Complete interrupt.
0x1
Wake on Receive Start or Receive
Complete interrupt.
Generic clock is enabled in all sleep modes. Any
interrupt can wake up the device.