Data Sheet

457
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
25.8.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: Enable-Protected, Write-Protected, Write-Synchronized
z Bit 31 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bit 30 – DORD: Data Order
This bit indicates the data order when a character is shifted out from the Data register.
0: MSB is transmitted first.
1: LSB is transmitted first.
This bit is not synchronized.
z Bit 29 – CPOL: Clock Polarity
This bit indicates the relationship between data output change and data input sampling in synchronous mode.
This bit is not synchronized.
Bit3130292827262524
DORD CPOL CMODE FORM[3:0]
Access R R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit2322212019181716
SAMPA[1:0] RXPO[1:0]
TXPO[1:0]
Access R/W R/W R/W R/W R R R/W R/W
Reset00000000
Bit151413121110 9 8
SAMPR[2:0]
IBON
Access R/W R/W R/W R R R R R
Reset00000000
Bit76543210
RUNSTDBY
MODE[2:0] ENABLE SWRST
Access R/W R R R/W R/W R/W R/W R/W
Reset00000000