Data Sheet

434
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
24.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
z Interrupt Flag Status and Clear register (INTFLAG)
z Address register (ADDR)
z Data register (DATA)
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Refer to “PAC – Peripheral Access
Controller” on page 41 for details.
24.5.9 Analog Connections
Not applicable.
24.6 Functional Description
24.6.1 Principle of Operation
The basic structure of the SERCOM serial engine is shown in Figure 24-2. Fields shown in capital letters are
synchronous to the system clock and accessible by the CPU, while fields with lowercase letters can be configured to run
on the GCLK_SERCOMx_CORE clock or an external clock.
Figure 24-2. SERCOM Serial Engine
The transmitter consists of a single write buffer and a shift register. The receiver consists of a two-level receive buffer and
a shift register. The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external
clock. Address matching logic is included for SPI and I
2
C operation.
Transmitter
Baud Rate Generator
= =
Selectable
Internal Clk
(GCLK)
Ext Clk
Receiver
Address Match
baud rate generator
tx shift register
rx shift register
rx bufferstatus
BAUD TX DATA ADDR/ADDRMASK
RX DATASTATUS
1/- /2- /16