Data Sheet

430
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
23.8.7 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18
Reset: 0x00000000
Property: -
z Bits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 27:24 – EVDx [x=11..8]: Channel x Event Detection
This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and
an interrupt request will be generated if INTENCLR/SET.EVDx is one.
When the event channel path is asynchronous, the EVDx interrupt flag will not be set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Event Detected Channel n interrupt flag.
z Bits 23:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 19:16 – OVRx [x=11..8]: Channel x Overrun
This flag is set on the next CLK_EVSYS cycle after an overrun channel condition occurs, and an interrupt request
will be generated if INTENCLR/SET.OVRx is one.
When the event channel path is asynchronous, the OVRx interrupt flag will not be set.
Bit 3130292827262524
EVD11 EVD10 EVD9 EVD8
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
OVR11 OVR10 OVR9 OVR8
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000