Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
10.5 AHB-APB Bridge
The AHB-APB bridge is an AHB slave, providing an interface between the high-speed AHB domain and the low-power
APB domain. It is used to provide access to the programmable control registers of peripherals (see “Product Mapping” on
page 28).
AHB-APB bridge is based on AMBA APB Protocol Specification V2.0 (ref. as APB4) including:
z Wait state support
z Error reporting
z Transaction protection
z Sparse data transfer (byte, half-word and word)
Additional enhancements:
z Address and data cycles merged into a single cycle
z Sparse data transfer also apply to read access
to operate the AHB-APB bridge, the clock (CLK_HPBx_AHB) must be enabled. See “PM – Power Manager” on page 117
for details.
Figure 10-1. APB Write Access.
T0 T1 T2 T3
Addr 1
Data 1
PADDR
PWRITE
PCLK
PSEL
PENABLE
PWDATA
PREADY
T0 T1 T2 T3
Addr 1
Data 1
PADDR
PWRITE
PCLK
PSEL
PENABLE
PWDATA
PREADY
T4 T5
Wait statesNo wait states