Data Sheet

399
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
22.8.10 Control
Name: CTRL
Offset: 0x24+x*0x80 [x=0..2]
Reset: 0x00000000
Property: Write-Protected
z Bits 31:0 – SAMPLING[31:0]: Input Sampling Mode
Configures the input sampling functionality of the I/O pin input samplers for pins configured as inputs via the Data
Direction register (DIR).
0: The I/O pin input synchronizer is disabled.
1: The I/O pin input synchronizer is enabled.
The input samplers are enabled and disabled in sub-groups of eight. Thus, if any pins within a byte request contin-
uous sampling, all pins in that eight pin sub-group will be continuously sampled.
Bit 3130292827262524
SAMPLING[31:24]
AccessWWWWWWWW
Reset00000000
Bit 2322212019181716
SAMPLING[23:16]
AccessWWWWWWWW
Reset00000000
Bit 151413121110 9 8
SAMPLING[15:8]
AccessWWWWWWWW
Reset00000000
Bit 76543210
SAMPLING[7:0]
AccessWWWWWWWW
Reset00000000