Data Sheet

395
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
22.8.6 Data Output Value Clear
This register allows the user to set one or more output I/O pin drive levels low, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle
(OUTTGL) and Data Output Value Set (OUTSET) registers.
Name: OUTCLR
Offset: 0x14+x*0x80 [x=0..2]
Reset: 0x00000000
Property: Write-Protected
z Bits 31:0 – OUTCLR[31:0]: Port Data Output Value Clear
0: The I/O pin output is driven low.
1: The I/O pin output is driven high.
Writing a zero to a bit has no effect.
Writing a one to a bit will clear the corresponding bit in the OUT register, which sets the output drive level low for
I/O pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via the Data
Direction register (DIR) and with pull enabled via the Pull Enable register (PULLEN), these bits will set the input
pull direction to an internal pull-down.
Bit 3130292827262524
OUTCLR[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
OUTCLR[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
OUTCLR[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
OUTCLR[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000