Data Sheet

391
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
22.8.2 Data Direction Clear
This register allows the user to set one or more I/O pins as an input, without doing a read-modify-write operation.
Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data
Direction Set (DIRSET) registers.
Name: DIRCLR
Offset: 0x04+x*0x80 [x=0..2]
Reset: 0x00000000
Property: Write-Protected
z Bits 31:0 – DIRCLR[31:0]: Port Data Direction Clear
0: The I/O pin direction is cleared.
1: The I/O pin direction is set.
Writing a zero to a bit has no effect.
Writing a one to a bit will clear the corresponding bit in the DIR register, which configures the I/O pin as an input.
Bit 3130292827262524
DIRCLR[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
DIRCLR[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
DIRCLR[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
DIRCLR[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000