Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z POSITION: Contains the trace write pointer and the wrap bit,
z MASTER: Contains the main trace enable bit and other trace control fields,
z FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits,
z BASE: Indicates where the SRAM is located in the processor memory map. This register is provided to enable
auto discovery of the MTB SRAM location, by a debug agent.
See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers.
10.4 High-Speed Bus System
10.4.1 Features
High-Speed Bus Matrix has the following features:
z Symmetric crossbar bus switch implementation
z Allows concurrent accesses from different masters to different slaves
z 32-bit data bus
z Operation at a one-to-one clock frequency with the bus masters