Data Sheet

360
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Data to be written to the NVM block are first written and stored in an internal buffer called the page buffer. The page
buffer contains the same number of bytes as an NVM page. Writes to the page buffer must be 16 or 32 bits. 8-bit writes
to the page buffer is not allowed, and will cause a system exception.
Both the NVM main array and the RWWEE array share the same page buffer. Writing to the NVM block via the AHB bus
is performed by a load operation to the page buffer. For each AHB bus write, the address is stored in the ADDR register.
After the page buffer has been loaded with the required number of bytes, the page can be written to the addressed
location by setting CMD to Write Page or RWWEE Write Page to write respectively the NVM main array or the RWWEE
array and setting the key value to CMDEX. The LOAD bit in the STATUS register indicates whether the page buffer has
been loaded or not. Before writing the page to memory, the accessed row must be erased.
By default, automatic page writes are enabled (MANW=0). This will trigger a write operation to the page addressed by
ADDR when the last location of the page is written.
Because the address is automatically stored in ADDR during the I/O bus write operation, the last given address will be
present in the ADDR register. There is no need to load the ADDR register manually, unless a different page in memory is
to be written.
Procedure for Manual Page Writes (MANW=1)
The row to be written must be erased before the write command is given.
z Write to the page buffer by addressing the NVM main address space directly
z Write the page buffer to memory: CMD=Write Page and CMDEX
z The READY bit in the INTFLAG register will be low while programming is in progress, and access through the AHB
will be stalled
Procedure for Automatic Page Writes (MANW=0)
The row to be written must be erased before the last write to the page buffer is performed.
Note that partially written pages must be written with a manual write.
z Write to the page buffer by addressing the NVM main address space directly.
z When the last location in the page buffer is written, the page is automatically written to NVM main address
space.
z INTFLAG.READY will be zero while programming is in progress and access through the AHB will be stalled.
21.6.5.4 Page Buffer Clear
The page buffer is automatically cleared to all ones after a page write is performed. If a partial page has been written and
it is desired to clear the contents of the page buffer, the Page Buffer Clear command can be used.
21.6.5.5 Erase Row
Before a page can be written, the row that contains the page must be erased. The Erase Row command can be used to
erase the desired row in the NVM main address space. The RWWEE Erase Row can be used to erase the desired row in
the RWWEE array. Erasing the row sets all bits to one. If the row resides in a region that is locked, the erase will not be
performed and the Lock Error bit in the Status register (STATUS.LOCKE) will be set.
Procedure for Erase Row
z Write the address of the row to erase ADDR. Any address within the row can be used.
z Issue an Erase Row command.
21.6.5.6 Lock and Unlock Region
These commands are used to lock and unlock regions as detailed in section “Region Lock Bits” on page 358.
21.6.5.7 Set and Clear Power Reduction Mode
The NVM Controller and block can be taken in and out of power reduction mode through the set and clear power
reduction mode commands. When the NVM Controller and block are in power reduction mode, the Power Reduction
Mode bit in the Status register (STATUS.PRM) is set.