Data Sheet

359
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
RWWEE address space directly, while other operations such as manual page writes and row erase must be performed
by issuing commands through the NVM Controller.
To issue a command, the CTRLA.CMD bits must be written along with the CTRLA.CMDEX value. When a command is
issued, INTFLAG.READY will be cleared until the command has completed. Any commands written while
INTFLAG.READY is low will be ignored. Read the CTRLA register description for more details.
The CTRLB register must be used to control the power reduction mode, read wait states and the write mode.
21.6.5.1 NVM Read
Reading from the NVM main address space is performed via the AHB bus by addressing the NVM main address space
or auxiliary address space directly. Read data is available after the configured number of read wait states (CTRLB.RWS)
set in the NVM Controller, has passed.
The number of cycles data are delayed to the AHB bus is determined by the read wait states. Examples of using zero
and one wait states are shown in Figure 21-5.
Reading the NVM main address space while a programming or erase operation is ongoing on the NVM main array
results in an AHB bus stall until the end of the operation. Reading the NVM main array does not stall the bus when the
RWWEE array is being programmed or erased.
Figure 21-5. Read Wait State Examples
21.6.5.2 RWWEE Read
Reading from the RWW EEPROM address space is performed via the AHB bus by addressing the RWWEE address
space directly. Refer to Figure 21-3 for details. Read timings are similar to regular NVM read timings when access size is
Byte or half-Word. The AHB data phase is twice longer in case of Word-size access. It is not possible reading the
RWWEE area while the NVM main array is being programmed or erased whereas the contrary is possible. The RWWEE
address space is not cached, therefore it is recommended to limit accesses to this area for performance and power
consumption considerations.
21.6.5.3 NVM Write
The NVM Controller requires that an erase must be done before programming. The entire NVM main address space and
the RWWEE address space can be erased by a debugger Chip Erase command. Alternatively, rows can be individually
erased by the Erase Row command or the RWWEE Erase row command to erase respectively the NVM main address
space and the RWWEE address space.
After programming, the region that the page resides in can be locked to prevent spurious write or erase sequences.
Locking is performed on a per-region basis, and so locking a region locks all pages inside the region.
Rd 0 Rd 1 Idle
Data 0 Data 1
1 Wait State
Rd 0
Rd 1
Idle
Data 0 Data 1
0 Wait States
AHB Command
AHB Slave Ready
AH B Slave D ata
AHB Command
AHB Slave Ready
AHB Slave Data