Data Sheet

35
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
writing a one to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register. An interrupt request
is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt
requests for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An
interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers
(SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt
enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority
field for each interrupt.
Table 10-3. Interrupt Line Mapping
Peripheral Source NVIC Line
EIC NMI – External Interrupt Controller NMI
PM – Power Manager 0
SYSCTRL – System Control 1
WDT – Watchdog Timer 2
RTC – Real Time Counter 3
EIC – External Interrupt Controller 4
NVMCTRL – Non-Volatile Memory Controller 5
DMAC - Direct Memory Access Controller 6
USB - Universal Serial Bus 7
EVSYS – Event System 8
SERCOM0 – Serial Communication Interface 0 9
SERCOM1 – Serial Communication Interface 1 10
SERCOM2 – Serial Communication Interface 2 11
SERCOM3 – Serial Communication Interface 3 12
SERCOM4 – Serial Communication Interface 4 13
SERCOM5 – Serial Communication Interface 5 14
TCC0 – Timer Counter for Control 0 15
TCC1 – Timer Counter for Control 1 16
TCC2 – Timer Counter for Control 2 17