Data Sheet

349
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
20.8.6 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x08
Reset: 0x00000000
Property: Write-Protected
z Bits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 17:0 – EXTINTx [x=17..0]: External Interrupt x Enable
0: The external interrupt x is disabled.
1: The external interrupt x is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the External Interrupt x Enable bit, which enables the external interrupt.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
EXTINT17 EXTINT16
AccessRRRRRRR/WR/W
Reset00000000
Bit 151413121110 9 8
EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000