Data Sheet

335
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
19.8.2.5 Next Descriptor Address
The DESCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name: DESCADDR
Offset: 0x0C
z Bits 31:0 – DESCADDR[31:0]: Next Descriptor Address
This bit group holds the SRAM address of the next descriptor. The value must be 128-bit aligned. If the value of
this SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to load the next trans-
fer descriptor.
Bit 3130292827262524
DESCADDR[31:24]
Bit 2322212019181716
DESCADDR[23:16]
Bit 151413121110 9 8
DESCADDR[15:8]
Bit 76543210
DESCADDR[7:0]