Data Sheet

332
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
19.8.2.2 Block Transfer Count
The BTCNT register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name: BTCNT
Offset: 0x02
z Bits 15:0 – BTCNT[15:0]: Block Transfer Count
This bit group holds the 16-bit block transfer count.
During a transfer, the internal counter value is decremented by one after each beat transfer. The internal counter is
written to the corresponding write-back memory section for the DMA channel when the DMA channel loses priority,
is suspended or gets disabled. The DMA channel can be disabled by a complete transfer, a transfer error or by
software.
Bit 151413121110 9 8
BTCNT[15:8]
Bit 76543210
BTCNT[7:0]