Data Sheet

326
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
19.8.1.21 Channel Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Channel Interrupt Enable Clear (CHINTENCLR) register.
Name: CHINTENSET
Offset: 0x4D
Reset: 0x00
Property: Write-Protected
z Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 2 – SUSP: Channel Suspend Interrupt Enable
0: The Channel Suspend interrupt is disabled.
1: The Channel Suspend interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Channel Suspend Interrupt Enable bit, which enables the Channel Suspend
interrupt.
z Bit 1 – TCMPL: Transfer Complete Interrupt Enable
0: The Channel Transfer Complete interrupt is disabled.
1: The Channel Transfer Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Channel Transfer Complete Interrupt Enable bit, which enables the Channel
Transfer Complete interrupt.
z Bit 0 – TERR: Transfer Error Interrupt Enable
0: The Channel Transfer Error interrupt is disabled.
1: The Channel Transfer Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Channel Transfer Error Interrupt Enable bit, which enables the Channel Trans-
fer Error interrupt.
Bit 76543210
SUSP TCMPL TERR
AccessRRRRRR/WR/WR/W
Reset00000000