Data Sheet

323
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bits 6:5 – LVL[1:0]: Channel Arbitration Level
These bits define the arbitration level used for the DMA channel. The available levels are shown in Table 19-9,
where a high level has priority over a low level. For further details on arbitration schemes, refer to “Arbitration” on
page 279.
These bits are not enable-protected.
0x13 TCC1 MC0 TCC1 Match/Compare 0 Trigger
0x14 TCC1 MC1 TCC1 Match/Compare 1 Trigger
0x15 TCC2 OVF TCC2 Overflow Trigger
0x16 TCC2 MC0 TCC2 Match/Compare 0 Trigger
0x17 TCC2 MC1 TCC2 Match/Compare 1 Trigger
0x18 TC3 OVF TC3 Overflow Trigger
0x19 TC3 MC0 TC3 Match/Compare 0 Trigger
0x1A TC3 MC1 TC3 Match/Compare 1 Trigger
0x1B TC4 OVF TC4 Overflow Trigger
0x1C TC4 MC0 TC4 Match/Compare 0 Trigger
0x1D TC4 MC1 TC4 Match/Compare 1 Trigger
0x1E TC5 OVF TC5 Overflow Trigger
0x1F TC5 MC0 TC5 Match/Compare 0 Trigger
0x20 TC5 MC1 TC5 Match/Compare 1 Trigger
0x21 TC6 OVF TC6 Overflow Trigger
0x22 TC6 MC0 TC6 Match/Compare 0 Trigger
0x23 TC6 MC1 TC6 Match/Compare 1 Trigger
0x24 TC7 OVF TC7 Overflow Trigger
0x25 TC7 MC0 TC7 Match/Compare 0 Trigger
0x26 TC7 MC1 TC7 Match/Compare 1 Trigger
0x27 ADC RESRDY ADC Result Ready Trigger
0x28 DAC EMPTY DAC Empty Trigger
0x29 I2S RX 0 I2S RX 0 Trigger
0x2A I2S RX 1 I2S RX 1 Trigger
0x2B I2S TX 0 I2S TX 0 Trigger
0x2C I2S TX 1 I2S TX 1 Trigger
Table 19-8. Peripheral Trigger Source (Continued)
Value Name Description