Data Sheet

322
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z Bits 23:22 – TRIGACT[1:0]: Trigger Action
These bits define the trigger action used for a transfer, as shown in Table 19-7.
Table 19-7. Trigger Action
z Bits 21:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 13:8 – TRIGSRC[5:0]: Peripheral Trigger Source
These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and trigger
modes, refer to “Transfer Triggers and Actions” on page 281 and Table 19-7.
TRIGACT[1:0] Name Description
0x0 BLOCK One trigger required for each block transfer
0x1 Reserved
0x2 BEAT One trigger required for each beat transfer
0x3 TRANSACTION One trigger required for each transaction
Table 19-8. Peripheral Trigger Source
Value Name Description
0x00 DISABLE Only software/event triggers
0x01 SERCOM0 RX SERCOM0 RX Trigger
0x02 SERCOM0 TX SERCOM0 TX Trigger
0x03 SERCOM1 RX SERCOM1 RX Trigger
0x04 SERCOM1 TX SERCOM1 TX Trigger
0x05 SERCOM2 RX SERCOM2 RX Trigger
0x06 SERCOM2 TX SERCOM2 TX Trigger
0x07 SERCOM3 RX SERCOM3 RX Trigger
0x08 SERCOM3 TX SERCOM3 TX Trigger
0x09 SERCOM4 RX SERCOM4 RX Trigger
0x0A SERCOM4 TX SERCOM4 TX Trigger
0x0B SERCOM5 RX SERCOM5 RX Trigger
0x0C SERCOM5 TX SERCOM5 TX Trigger
0x0D TCC0 OVF TCC0 Overflow Trigger
0x0E TCC0 MC0 TCC0 Match/Compare 0 Trigger
0x0F TCC0 MC1 TCC0 Match/Compare 1 Trigger
0x10 TCC0 MC2 TCC0 Match/Compare 2 Trigger
0x11 TCC0 MC3 TCC0 Match/Compare 3 Trigger
0x12 TCC1 OVF TCC1 Overflow Trigger