Data Sheet

Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181G–SAM-D21_Datasheet–09/2015

19.8.1.18 Channel Control A

Name: CHCTRLA

Offset: 0x40

Reset: 0x00

Property: Enable-Protected, Write-Protected

z Bits 7:2 – Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to

zero when this register is written. These bits will always return zero when read.

z Bit 1 – ENABLE: Channel Enable

0: DMA channel is disabled.

1: DMA channel is enabled.

Writing a zero to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer

is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst

transfer is completed.

Writing a one to this bit will enable the DMA channel.

This bit is not enable-protected.

z Bit 0 – SWRST: Channel Software Reset

0: There is no reset operation ongoing.

1: The reset operation is ongoing.

Writing a zero to this bit has no effect.

Writing a one to this bit resets the channel registers to their initial state. The bit can be set when the channel is dis-

abled (ENABLE = 0). Writing a one to this bit will be ignored as long as the channel is enabled (ENABLE = 1). This

bit is automatically cleared when the reset is completed.

Writing a one to this bit when the corresponding DMA channel is disabled (ENABLE is zero), resets all registers for

the corresponding DMA channel to their initial state If the corresponding DMA channel is enabled, the reset

request will be ignored.

Bit 76543210

ENABLE SWRST

AccessRRRRRRR/WR/W

Reset00000000