Data Sheet

314
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
19.8.1.13 Pending Channels
Name: PENDCH
Offset: 0x2C
Reset: 0x00000000
Property: -
z Bits 31:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 11:0 – PENDCHx [x=11..0]: Pending Channel x
This bit is cleared when trigger execution defined by channel trigger action settings for DMA channel x is started,
when a bus error for DMA channel x is detected or when DMA channel x is disabled. For details on trigger action
settings, refer to Table 19-7.
This bit is set when a transfer is pending on DMA channel x.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
PENDCH11 PENDCH10 PENDCH9 PENDCH8
AccessRRRRRRRR
Reset00000000
Bit 76543210
PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0
AccessRRRRRRRR
Reset00000000