Data Sheet

305
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
19.8.1.7 QOS Control
Name: QOSCTRL
Offset: 0x0E
Reset: 0x15
Property: Enable-Protected, Write-Protected
z Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 5:4 – DQOS[1:0]: DATA Quality of Service
These bits define the SRAM quality of service of the DMAC DATA master. Refer to “SRAM Quality of Service” on
page 39.
z Bits 3:2 – FQOS[1:0]: Fetch Quality of Service
These bits define the SRAM quality of service of the DMAC Fetch master. Refer to “SRAM Quality of Service” on
page 39.
z Bits 1:0 – WBQOS[1:0]: WB Quality of Service
These bits define the SRAM quality of service of the DMAC WB master. Refer to “SRAM Quality of Service” on
page 39.
Bit 76543210
DQOS[1:0] FQOS[1:0] WBQOS[1:0]
Access R R R/W R/W R/W R/W R/W R/W
Reset00010101