Data Sheet

299
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
19.8.1.2 CRC Control
Name: CRCCTRL
Offset: 0x02
Reset: 0x0000
Property: Enable-Protected, Write-Protected
z Bits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 13:8 – CRCSRC[5:0]: CRC Input Source
These bits select the input source for generating the CRC, as shown in Table 19-3. The selected source is locked
until either the CRC generation is completed or the CRC module is disabled. This means the CRCSRC cannot be
modified when the CRC operation is ongoing. The lock is signaled by the CRCBUSY status bit. CRC generation
complete is generated and signaled from the selected source when used with the DMA channel.
Table 19-3. CRC Input Source
z Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 3:2 – CRCPOLY[1:0]: CRC Polynomial Type
These bits select the CRC polynomial type, as shown in Table 19-4.
Bit 151413121110 9 8
CRCSRC[5:0]
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Bit 76543210
CRCPOLY[1:0] CRCBEATSIZE[1:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
CRCSRC[5:0] Name Description
0x0 NOACT No action
0x1 IO I/O interface
0x2-0x1F Reserved
0x20-0x3F CHN DMA channel n