Data Sheet
297
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
19.8.1 DMAC Registers
19.8.1.1 Control
Name: CTRL
Offset: 0x00
Reset: 0x0000
Property: Enable-Protected, Write-Protected
z Bits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 11:8 – LVLENx [x=3..0]: Priority Level x Enable
0: Transfer requests for Priority level x will not be handled.
1: Transfer requests for Priority level x will be handled.
When this bit is set, all requests with the corresponding level will be fed into the arbiter block. When cleared, all
requests with the corresponding level will be ignored.
For details on arbitration schemes, refer to “Arbitration” on page 279 section.
These bits are not enable-protected.
z Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 2 – CRCENABLE: CRC Enable
0: The CRC module is disabled.
1: The CRC module is enabled.
Writing a zero to this bit will disable the CRC module if the CRC Status Busy bit in the CRC Status register (CRC-
STATUS.CRCBUSY) is zero. If the CRCSTATUS.CRCBUSY is one, the write will be ignored and the CRC module
will not be disabled.
Writing a one to this bit will enable the CRC module.
This bit is not enable-protected.
z Bit 1 – DMAENABLE: DMA Enable
0: The peripheral is disabled.
1: The peripheral is enabled.
Writing a zero to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer
is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst
transfer is completed.
Bit 151413121110 9 8
LVLEN3 LVLEN2 LVLEN1 LVLEN0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
CRCENABLE DMAENABLE
SWRST
AccessRRRRRR/WR/WR/W
Reset00000000