Data Sheet

291
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
CRC can be performed on any data by loading them into the CRC module using the CPU and writing the data to the
CRCDATAIN register. Using this method, an arbitrary number of bytes can be written to the register by the CPU, and
CRC is done continuously for each byte. This means if a 32-bit data is written to the CRCDATAIN register the CRC
module takes 4 cycles to calculate the CRC. The CRC complete is signaled by the CRCBUSY bit in the CRCSTATUS
register. New data can be written only when CRCBUSY flag is not set.
19.6.4 DMA Operation
Not applicable.
19.6.5 Interrupts
The DMAC has the following interrupt sources:
z Transfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding channel. Refer to
“Data Transmission” on page 280 for details.
z Transfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an invalid descriptor
has been fetched. Refer to “Error Handling” on page 284 for details.
z Channel Suspend (SUSP): Indicates that the corresponding channel has been suspended. Refer to “Channel
Suspend” on page 285
and “Data Transmission” on page 280 for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Channel Interrupt Flag Status and
Clear (CHINTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by
writing a one to the corresponding bit in the Channel Interrupt Enable Set (CHINTENSET) register, and disabled by
writing a one to the corresponding bit in the Channel Interrupt Enable Clear (CHINTENCLR) register. An interrupt request
is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains
active until the interrupt flag is cleared, the interrupt is disabled, the DMAC is reset or the corresponding DMA channel is
reset. See CHINTFLAG for details on how to clear interrupt flags. All interrupt requests are ORed together on system
level to generate one combined interrupt request to the NVIC. Refer to “Nested Vector Interrupt Controller” on page 34
for details.
The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with pending interrupts
and must read the Channel Interrupt Flag Status and Clear (CHINTFLAG) register to determine which interrupt condition
is present for the corresponding channel. It is also possible to read the Interrupt Pending register (INTPEND), which
provides the lowest channel number with pending interrupt and the respective interrupt flags.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 34 for details.
19.6.6 Events
The DMAC can generate the following output events:
z Channel (CH): Generated when a block transfer for a given channel has been completed, or when a beat transfer
within a block transfer for a given channel has been completed. Refer to “Event Output Selections” on page 289 for
details.
Writing a one to the Channel Control B Event Output Enable bit (CHCTRLB.EVOE) enables the corresponding output
event configured in the Event Output Selection bit group in the Block Transfer Control register (BTCTRL.EVOSEL).
Writing a zero to CHCTRLB.EVOE disables the corresponding output event. Refer to “EVSYS – Event System” on page
406 for details on configuring the event system.
The DMAC can take the following actions on an input event:
z Transfer and Periodic Transfer Trigger (TRIG): normal transfer or periodic transfers on peripherals are enabled
z Conditional Transfer Trigger (CTRIG): conditional transfers on peripherals are enabled
z Conditional Block Transfer Trigger (CBLOCK): conditional block transfers on peripherals are enabled
z Channel Suspend Operation (SUSPEND): suspend a channel operation
z Channel Resume Operation (RESUME): resume a suspended channel operation