Data Sheet

286
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Figure 19-10.Channel Suspend/Resume Operation
19.6.3.4 Event Input Actions
The event input actions are available only for channels supporting event inputs. For details on channels with event input
support, refer to Table 23-6 and Table 23-4.
The Event Actions bits in the Channel Control B register (CHCTRLB.EVACT) specify the actions the DMA will take on an
input event. Before using event actions, the event controller must be configured first and the corresponding Channel
Event Input Enable bit (CHCTRLB.EVIE) must be set. The DMA supports only resynchronized events. For details on how
to configure the resynchronized event path, refer to the Event System.
Normal transfer: When this event action is selected for a channel, the event input is used to trigger a beat or burst
transfer on peripherals.
The transfer trigger is selected by setting the Trigger Source bits in Channel Control B register to zero
(CHCTRLB.TRIGSRC). The event is acknowledged as soon as the event is received. When received, the Channel
Pending status bit is set (CHSTATUS.PEND). If the event is received while the channel is pending, the event trigger is
lost. Figure 19-11 shows an example where beat transfers are enabled by internal events.
Figure 19-11.Beat Event Trigger Action
Periodic transfers: When this event action is selected for a channel, the event input is used to trigger a transfer on
peripherals with pending transfer requests. This type of event is intended to be used with peripheral triggers for example,
for timed communication protocols or periodic transfers between peripherals, as examples. The peripheral trigger is
selected by the Trigger Source bits in the Channel Control B register (CHCTRLB.TRIGSRC).
The event is acknowledged as soon as the event is received. The peripheral trigger request is stored internally when the
previous trigger action is completed (i.e. channel is not pending) and when an active event is received. If the peripheral
trigger is active, the DMA will wait for an event before the peripheral trigger is internally registered. When both event and
peripheral transfer trigger are active, the Channel Pending status bit is set (CHSTATUS.PEND). A software trigger will
now trigger a transfer.
Figure 19-12 shows an example where the peripheral beat transfers are enabled by periodic events.
Descriptor 0
(suspend disabled)
Memory Descriptor
Transfer
Resume Command
Descriptor 1
(suspend enabled)
Descriptor 2
(suspend enabled)
Suspend skipped
Channel
suspended
Descriptor 3
(last)
Fetch
Block
Transfer 0
Block
Transfer 1
Block
Transfer 2
Block
Transfer 3
CHENn
BEAT BEAT BEAT
Block Transfer
BEAT BEAT BEAT
Block Transfer
Event
BUSYCHn
CHENn
Data Transfer
PENDCHn
Trigger Lost
Peripheral Trigger