Data Sheet

283
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
register(BTCTRL.STEPSEL) to one, and the Address Increment Step Size bit group in the Block Transfer Control
register (BTCTRL.STEPSIZE), to the desired step size. If BTCTRL.STEPSEL is zero, the step size for the source
incrementation will be the size of one beat.
When source address incrementation is configured (BTCTRL.SRCINC is one), SRCADDR must be set to the source
address of the last beat transfer in the block transfer. The source address should be calculated as follows:
z SRCADDRSTART is the source address of the first beat transfer in the block transfer
z BTCNT is the initial number of beats remaining in the block transfer
z BEATSIZE is the configured number of bytes in a beat
z STEPSIZE is the configured number of beats for each incrementation
Figure 19-8 shows an example where DMA channel 0 is configured to increment the source address by one beat
(BTCTRL.SRCINC is one) after each beat transfer, and DMA channel 1 is configured to increment source address by two
beats (BTCTRL.SRCINC is one, BTCTRL.STEPSEL is one, and BTCTRL.STEPSIZE is 0x1). As the destination address
for both channels are peripherals, destination incrementation is disabled(BTCTRL.DSTINC is zero).
Figure 19-8. Source Address Increment
Incrementation for the destination address of a block transfer is enabled by writing the Destination Address
Incrementation Enable bit in the Block Transfer Control register (BTCTRL.DSTINC) to one. The step size of the
incrementation is configurable and can be chosen by writing BTCTRL.STEPSEL to zero, and BTCTRL.STEPSIZE to the
desired step size. If BTCTRL.STEPSEL is one, the step size for the destination incrementation will be the size of one
beat.
When destination address incrementation is configured (BTCTRL.DSTINC is one), SRCADDR must be set to the
destination address of the last beat transfer in the block transfer. The destination address should be calculated as
follows:
z DSTADDRSTART is the destination address of the first beat transfer in the block transfer
z BTCNT is the initial number of beats remaining in the block transfer
z BEATSIZE is the configured number of bytes in a beat
z STEPSIZE is the configured number of beats for each incrementation
Figure 19-9 shows an example where DMA channel 0 is configured to increment destination address by one beat
(BTCTRL.DSTINC is one) and DMA channel 1 is configured to increment destination address by two beats
(BTCTRL.DSTINC is one, BTCTRL.STEPSEL is zero, and BTCTRL.STEPSIZE is 0x1). As the source address for both
channels are peripherals, source incrementation is disabled(BTCTRL.SRCINC is zero).
, where BTCTRL.STEPSEL is one
, where BTCTRL.STEPSEL is zero
, where BTCTRL.STEPSEL is zero
, where BTCTRL.STEPSEL is one
SRCADDR SRCADDR
START
BTCNT BEATSIZE 1+()2
STEPSIZE
⋅⋅+=
SRCADDR SRCADDR
START
BTCNT BEATSIZE 1+()⋅+=
DMA Channel 0
DMA Channel 1
PERIPHERAL 0
PERIPHERAL 1
{a,b}
{c,e}
SRC Data Buffer
a
b
c
d
e
f
DSTADDR DSTADDR
START
BTCNT BEATSIZE 1+()2
STEPSIZE
⋅⋅+=
DSTADDR DSTADDR
START
BTCNT BEATSIZE 1+()⋅+=