Data Sheet
276
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
19.6.2 Basic Operation
19.6.2.1 Initialization
The following DMAC registers are enable-protected, meaning that they can only be written when the DMAC is disabled
(CTRL.DMAENABLE is zero):
z Descriptor Base Memory Address (BASEADDR) register
z Write-Back Memory Base Address (WRBADDR) register
The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and CRC are
disabled (CTRL.DMAENABLE and CTRL.CRCENABLE is zero):
z Software Reset bit in Control register (CTRL.SWRST)
The following DMA channel register is enable-protected, meaning that it can only be written when the corresponding
DMA channel is disabled (CHCTRLA.ENABLE is zero):
z Channel Control B (CHCTRLB) register, except the Command (CHCTRLB.CMD) and Channel Arbitration Level
(CHCTRLB.LVL) bits
The following DMA channel bit is enable-protected, meaning that it can only be written when the corresponding DMA
channel is disabled:
z Channel Software Reset bit in Channel Control A register (CHCTRLA.SWRST)
The following CRC registers are enable-protected, meaning that they can only be written when the CRC is disabled
(CTRL.CRCENABLE is zero):
z CRC Control (CRCCTRL) register
z CRC Checksum (CRCCHKSUM) register
Enable-protection is denoted by the Enable-Protected property in the register description.
Before the DMAC is enabled, it must be configured, as outlined by the following steps:
z The SRAM address of where the descriptor memory section is located must be written to the Description Base
Address (BASEADDR) register
z The SRAM address of where the write-back section should be located must be written to the Write-Back Memory
Base Address (WRBADDR) register
z Priority level x of the arbiter can be enabled by writing a one to the Priority Level x Enable bit in the Control
register(CTRL.LVLENx)
Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must be configured,
as outlined by the following steps:
z DMA channel configurations
z The channel number of the DMA channel to configure must be written to the Channel ID (CHID) register
z Trigger action must be selected by writing the Trigger Action bit group in the Channel Control B register
(CHCTRLB.TRIGACT)
z Trigger source must be selected by writing the Trigger Source bit group in the Channel Control B register
(CHCTRLB.TRIGSRC)
z Transfer Descriptor
z The size of each access of the data transfer bus must be selected by writing the Beat Size bit group in the
Block Transfer Control register (BTCTRL.BEATSIZE)
z The transfer descriptor must be made valid by writing a one to the Valid bit in the Block Transfer Control
register (BTCTRL.VALID)
z Number of beats in the block transfer must be selected by writing the Block Transfer Count (BTCNT)
register
z Source address for the block transfer must be selected by writing the Block Transfer Source Address
(SRCADDR) register