Data Sheet

256
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
18.8.13 Interrupt Enable Set - MODE2
Name: INTENSET
Offset: 0x07
Reset: 0x00
Property: Write-Protected
z Bit 7 – OVF: Overflow Interrupt Enable
0: The overflow interrupt is disabled.
1: The overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt.
z Bit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The synchronization ready interrupt is disabled.
1: The synchronization ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt bit and enable the Synchronization Ready
interrupt.
z Bits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 0 – ALARM: Alarm 0 Interrupt Enable
0: The alarm 0 interrupt is disabled.
1: The alarm 0 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Alarm 0 Interrupt Enable bit and enable the Alarm 0 interrupt.
Bit 76543210
OVF SYNCRDY
ALARM0
AccessR/WR/WRRRRRR/W
Reset00000000