Data Sheet

255
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
18.8.12 Interrupt Enable Set - MODE1
Name: INTENSET
Offset: 0x07
Reset: 0x00
Property: Write-Protected
z Bit 7 – OVF: Overflow Interrupt Enable
0: The overflow interrupt is disabled.
1: The overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow interrupt bit and enable the Overflow interrupt.
z Bit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The synchronization ready interrupt is disabled.
1: The synchronization ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit and enable the Synchronization
Ready interrupt.
z Bits 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 1:0 – CMPx [x=1..0]: Compare x Interrupt Enable
0: The compare x interrupt is disabled.
1: The compare x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Compare x Interrupt Enable bit and enable the Compare x interrupt.
Bit 76543210
OVF SYNCRDY
CMP1 CMP0
AccessR/WR/WRRRRR/WR/W
Reset00000000