Data Sheet

243
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
18.8.2 Control - MODE1
Name: CTRL
Offset: 0x00
Reset: 0x0000
Property: Enable-Protected, Write-Protected, Write-Synchronized
z Bits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 11:8 – PRESCALER[3:0]: Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock
(CLK_RTC_CNT).
These bits are not synchronized.
Table 18-6. Prescaler
Bit 151413121110 9 8
PRESCALER[3:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
MODE[1:0] ENABLE SWRST
AccessRRRRR/WR/WR/WW
Reset00000000
PRESCALER[3:0] Name Description
0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1
0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2
0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4
0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8
0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16
0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32
0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64
0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128
0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256
0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512
0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024
0xB-0xF Reserved