Data Sheet

237
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
18.7 Register Summary
The register mapping depends on the Operating Mode bits in the Control register (CTRL.MODE). The register summary
is presented for each of the three modes.
Table 18-1. MODE0 - Mode Register Summary
Table 18-2. MODE1 - Mode Register Summary
Offset Name
Bit
Pos.
0x00
CTRL
7:0 MATCHCLR MODE[1:0] ENABLE SWRST
0x01 15:8
PRESCALER[3:0]
0x02
READREQ
7:0
ADDR[5:0]
0x03 15:8 RREQ RCONT
0x04
EVCTRL
7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0
0x05 15:8 OVFEO
CMPEO0
0x06 INTENCLR 7:0 OVF SYNCRDY
CMP0
0x07 INTENSET 7:0 OVF SYNCRDY
CMP0
0x08 INTFLAG 7:0 OVF SYNCRDY
CMP0
0x09 Reserved
0x0A STATUS 7:0 SYNCBUSY
0x0B DBGCTRL 7:0 DBGRUN
0x0C FREQCORR 7:0 SIGN VALUE[6:0]
0x0D
...
0x0F
Reserved
0x10
COUNT
7:0 COUNT[7:0]
0x11 15:8 COUNT[15:8]
0x12 23:16 COUNT[23:16]
0x13 31:24 COUNT[31:24]
0x14
...
0x17
Reserved
0x18
COMP0
7:0 COMP[7:0]
0x19 15:8 COMP[15:8]
0x1A 23:16 COMP[23:16]
0x1B 31:24 COMP[31:24]
Offset Name
Bit
Pos.
0x00
CTRL
7:0 MODE[1:0] ENABLE SWRST
0x01 15:8
PRESCALER[3:0]
0x02
READREQ
7:0
ADDR[5:0]
0x03 15:8 RREQ RCONT
0x04
EVCTRL
7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0
0x05 15:8 OVFEO
CMPEO1 CMPEO0
0x06 INTENCLR 7:0 OVF SYNCRDY
CMP1 CMP0
0x07 INTENSET 7:0 OVF SYNCRDY
CMP1 CMP0