Data Sheet

223
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
17.8.3 Early Warning Interrupt Control
Name: EWCTRL
Offset: 0x2
Reset: 0x0X
Property: Enable-Protected, Write-Protected
z Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 3:0 – EWOFFSET[3:0]: Early Warning Interrupt Time Offset
These bits determine the number of GCLK_WDT clocks in the offset from the start of the watchdog time-out period
to when the Early Warning interrupt is generated. The Early Warning Offset is defined in Table 17-6. These bits
are loaded from NVM User Row at startup. Refer to “NVM User Row Mapping” on page 30 for more details.
Table 17-6. Early Warning Interrupt Time Offset
Bit 76543210
EWOFFSET[3:0]
AccessRRRRR/WR/WR/WR/W
Reset0000XXXX
EWOFFSET[3:0] Description
0x0 8 clock cycles
0x1 16 clock cycles
0x2 32 clock cycles
0x3 64 clock cycles
0x4 128 clock cycles
0x5 256 clock cycles
0x6 512 clock cycles
0x7 1024 clock cycles
0x8 2048 clock cycles
0x9 4096 clock cycles
0xA 8192 clock cycles
0xB 16384 clock cycles
0xC-0xF Reserved